1. Field of the Invention
The present invention relates to programming an alternate-metal virtual-ground (AMG) EPROM or flash memory and, more particularly, to a method for programming these memories when cells of the array are formed to store multiple bits of data, i.e., more than a logic "1" and a logic "0".
2. Description of the Related Art
An alternate-metal virtual-ground (AMG) array architecture is a type of non-volatile memory architecture that is characterized by metal which only contacts every other bit line of the array. The AMG array architecture can be utilized with both U-V erasable EPROMs as well as flash memories.
FIG. 1 shows a portion of a conventional AMG array 10. As shown in FIG. 1, array 10 includes a plurality of contacted bit lines BLC, a plurality of non-contacted bit lines BLU formed so that one non-contacted bit line BLU is positioned between each pair of contacted bit lines BLC, a plurality of memory cells 12, and a plurality of access transistors 14. As shown, the contacted bit lines BLC directly contact a metal line ML, while the non-contacted bit lines BLU contact a metal line ML via one of the access transistors 14.
Memory cells 12 are arranged in columns and rows so that a predetermined number of cells 12 are formed between each pair of contacted and non-contacted bit lines BLC and BLU. Access transistors 14, on the other hand, are arranged in columns and rows so that in each row only one transistor 14 is formed between every other pair of contacted and non-contacted bit lines BLC and BLU.
Array 10 further includes a series of word lines WL1-WLn which are formed so that one word line WL is formed over each of the memory cells 12 in a row of memory cells. As is well known, the portion of the word line 18 which is formed over each memory cell 12 functions as the control gate of that memory cell. Similarly, the access transistors 14 in a row of access transistors 14 share one of four access lines AC1-AC4.
A cell in array 10 is conventionally programmed to store one bit of data by selecting the cell to be programmed, and then applying a programming voltage to the word line that corresponds to the cell to be programmed. For example, to program cell A, the contacted bit line BLC that adjoins cell A is held at an intermediate voltage Vd (approximately 5-7 V), while the contacted bit line BLC positioned on the opposite side of cell A is held at ground Vss. The remaining contacted bit lines BLC are allowed to float. In addition, access lines AC2 and AC3 are biased to the supply voltage Vcc (approximately 5 V), while access lines AC1 and AC4 are held at ground Vss. This, in turn, pulls the non-contacted bit line BLU that contacts cell A down to ground Vss.
The programming voltage Vpp (approximately 12 V) is then applied to word line WL1, while the remaining word lines WL2-WLn are grounded. These bias conditions result in current flow as shown by the arrow in FIG. 1, which results in electron injection from the drain of cell A to the floating gate of cell A, thus programming cell A.
One drawback to programming memory cells 12 as described above is that only one bit of data can be programmed into a cell, and only one cell in a column of cells can be programmed at any one time. Although it would appear that multiple cells in a column could be simultaneously programmed by applying the programming voltage Vpp to the word lines WL2-WLn that correspond to each cell in the column to be programmed, the high current requirements of each cell during programming (approximately 400 mA) preclude this. Thus, there is a need for a method of programming multiple cells in a column of an AMG array at the same time.